1. Field of the Invention
Several aspects of the present invention relate to an organic TFT inverter arrangement and to an organic TFT logic-gate arrangement comprising an organic TFT inverter arrangement.
2. Description of the Related Art
Inkjet organic thin-film transistors (OTFTs) have attracted much attention in recent years, because of the advance in solution-processable materials and inkjet fabrication techniques. Inkjet OTFT technology significantly reduces the cost of fabrication by depositing the material at only the desired places, thereby cutting wastage in material and reducing the process turn-around time. At the same time a significant amount of research effort has been directed to improving the electrical characteristics of OTFTs to a level achieved by amorphous silicon technology, its inorganic counterpart.
The electrical performance of inkjet OTFTs has been limited by, for example, low drain-source current (IDS) on/off ratio, poor sub-threshold slope (ΔIDS/ΔVGS), poor saturation in the output characteristics (IDS VS. VDS) and the existence of p-channel devices only, though this latter limitation has more recently been overcome. These limitations do not apply to technologies such as crystalline silicon transistor technology.
Examples of a basic known OTFT inverter arrangement are shown in FIG. 1. FIG. 1(a) gives the general circuit symbol for an inverter arrangement, fed by power supply lines VDD and VSS, where VDD>VSS, while FIGS. 1(b)-1(d) show more detailed constructions of such an inverter arrangement. FIG. 1(b) shows a p-channel OTFT device driving a purely resistive load and FIGS. 1(c) and (d) show p-channel OTFT devices driving a transistor load. In the case of FIG. 1(c) the load transistor is a diode connected p-channel device (gate connected to drain), while in FIG. 1(d) the load transistor is a p-channel device connected as an active load. The active load accepts a bias voltage at the gate that provides further control to the output voltage.
It is often desirable to optimise the size of the driver and load transistors in such an inverter arrangement, in order to provide a gain greater than unity and a sufficiently wide output swing. The latter is important if a wide noise margin is to be achieved. Unfortunately, the limitations of existing OTFTs make it difficult to meet these criteria. As a result, many researchers have proposed additional stages, such as a level-shifter in order to boost the gain before or after a conventional OTFT inverter stage. Example of this solution will now be described with reference to FIGS. 2 and 3.
In FIG. 2 a level-shifter is included before the inverter-stage. FIG. 2(a) is, again, the general circuit symbol for this arrangement, while FIGS. 2(b) and (c) are detailed embodiments of this arrangement. FIG. 2(b) is an arrangement published by H. Gerwin, et al., in their paper “Flexible active matrix displays and shift registers based on solution-processed organic transistors” in Nature Materials, published in 2004. The first stage acts as a voltage divider through the use of series-connected p-channel OTFTs working in their saturation region. The second stage is the inverter that uses a diode-connected OTFT load. The FIG. 2(c) example works in a similar fashion, but is based around an active OTFT load in the inverter stage. FIG. 2(c) is taken from H. Klauk, et al, “Pentacene organic thin-film transistors and ICs”, Solid Stage Technology, Vol. 43, Part 3, pp 63-67, (2000).
In FIG. 3 the level-shifter is added after the inverter stage. The FIG. 3(b) example is published in J. Krumm, et al, “A polymer transistor circuit using PDHTT”, IEEE Electron Device Letters, Vol. 25, No. 6 (June 2004). The level-shifter stage works as a voltage follower that fed from the output of the inverter stage. In FIG. 3(c), which is taken from H. Klauk, et al, “Pentacene organic transistors and ring oscillators on glass on flexible polymeric substrates”, Applied Physics Letters, Vol. 82, No. 23, pp 4175-4177 (2003), a similar voltage-follower level-shifter stage is employed, but in this case it is driven from the output of an active OTFT load in the inverter stage, instead of from a diode-connected OTFT load, which is the case in the FIG. 3(b) example. In addition the gate of the bias transistor in the level-shifter stage is fed from a different voltage supply from that of the inverter stage.
In both of these examples, the level-shifter stage ensures that high-level voltages can appear on the overall output terminal (“OUT”) by providing a voltage rail VLS for the level-shifter stage, which is higher than the inverter voltage rail VDD used for the inverter stage.